As the trend in semiconductors continues towards reduced critical dimensions, integrated circuits involving millions of transistors on a single chip have become commonplace. Due to the large number of devices on a single chip, an entire industry has evolved specifically to supply the semiconductor industry with software and hardware tools to automate much of the process of integrated circuit design.
Electronic design automation (EDA) tools are computer-based tools that assist through automation of procedures that would otherwise be performed manually. Simulation of proposed design functionality and synthesis of integrated circuit logic and layout are two examples.
In semiconductor integrated circuit fabrication, a contact is formed to electrically connect an active region or a conductive layer formed in a semiconductor substrate with a metal interconnect line formed on a dielectric layer disposed between the interconnect line and the substrate. In a back end of line (BEOL) structure, many metallization levels may be interconnected by via levels. With development of high density integrated circuit technology, more components require placement on a chip, increasing complexity of the fabrication process, including the design and placement of vias. EDA tools provide valuable assistance in this regard. However, challenges still remain regarding appropriate via sizing and placement. It is therefore desirable to have improvements to address the aforementioned challenges.